a few hours into writing a PSRAM memory controller i can confidently declare: DRAM has been a mistake. we should all be using on-chip SRAM only. if your working set doesn't fit into it, just get a bigger die
I spent more than a few brain cycles on thinking about, how far you could shrink thyristor-like structures in order to implement high density, low structure count SRAM.
@whitequark The cyclist in me has so many jokes about this that will completely fail to be delivered outside of the tiniest niche. stacking sram chiplets is our destiny though.
Jul 3, 2026, 10:08 AM@cararemixed @whitequark came here for this grip shift joke
@cararemixed @whitequark tiny niche member checking in
@whitequark I've thought for a while that it's real dumb how x86 CPUs blew way past 640KiB of L3 cache ages ago and yet at no point has anyone ever thought to let us boot from it.
Jul 3, 2026, 9:14 AM@thepi @whitequark you can run from just cache, I *think*.
Eg, like this: https://doc.coreboot.org/getting_started/architecture.html#cache-as-ram
Jul 3, 2026, 9:22 AM@thepi @whitequark oh, perhaps more info: https://pete.akeo.ie/2011/08/ubrx-l2-cache-as-instruction-ram.html?m=0
tbh, reading this it's not clear to me that cache-as-ram really works or if you can use the L3 that way. It certainly seems fiddly!
Jul 3, 2026, 9:19 AM@whitequark graphcore
Jul 3, 2026, 9:19 AM@whitequark more like cerebras ig
Jul 3, 2026, 9:21 AM@whitequark > a 9950X3D2 wrote this post
@whitequark the cerebras mindset
@atomicthumbs @whitequark Just 44 GiB of SRAM on a chip. You will certainly not regret your million-core dinner-plate size chip.
@chrisvest Amdahl's Dream Is Alive
@whitequark glares at cpu manufacturers
Dave Conroy built an experimental Alpha workstation at DEC SRC that only had SRAM
Jul 3, 2026, 2:14 PM@bitsavers @whitequark how much progress from Cray-level size, power and cooling have such systems made in theory? Cray 1 through 4 had all-SRAM main system memory I think. They were fast but also a bit inconvenient for home use.