Login
You're viewing the assemblag.es public feed.
  • Sep 16, 2026, 9:11 PM

    @mcc I guess you still need a way to detect how many spare bits there are. AMD already has 52 bit addressing, and Intel is looking at 57 bits.

    So many systems have done this pointer tagging cheat in the past. None of them survived to today. I get the feeling it always comes with greater hidden costs.

    💬 2🔄 1⭐ 0

Replies

  • 💬 3🔄 0⭐ 0
  • Sep 16, 2026, 9:25 PM

    @mcc @hyc we have a gamedev friend and a platform ABI friend who are always teasing each other about the other party stealing their pointer bits

    💬 2🔄 0⭐ 0
  • Sep 16, 2026, 9:26 PM

    @mcc @hyc we definitely think it's less common than it used to be for language runtimes in languages that aren't made by OS vendors, perhaps due to portability concerns, but we can attest for certain that it is still a thing that happens

    💬 0🔄 0⭐ 0
  • Sep 16, 2026, 9:28 PM

    @mcc @hyc we are not ourselves experts on it, we do find it very easy to believe that it has hidden costs

    it's just that if your goal either involves a very high level of vertical integration, or is a very tightly focused single-purpose thing, that can be mitigated

    💬 0🔄 0⭐ 0
  • 💬 1🔄 0⭐ 2
  • 💬 0🔄 0⭐ 0
  • 💬 1🔄 1⭐ 1
  • Sep 17, 2026, 2:40 AM

    @natevw @Catfish_Man @ireneista @mcc @hyc @MaddieM4 Now @mikeash is in charge of the pointer bit stealing in the Objective-C and Swift runtimes. I moved over to kernel security, currently stealing pointer bits inside the virtual memory metadata.

    The recent increase in RAM prices has made these tricks even more commercially relevant, unfortunately.

    💬 0🔄 0⭐ 5
  • 💬 0🔄 1⭐ 2
  • 💬 1🔄 1⭐ 0
  • Sep 16, 2026, 11:25 PM

    @hyc Ideally, you'd have a fallback for systems that don't give you enough bits for the tagging you want

    💬 1🔄 0⭐ 0
  • Sep 17, 2026, 2:59 AM

    @mcc sounds like an expensive exercise in planned obsolescence. System capacities keep growing, and just like 32bit RAM sizes eventually grew to fill the entire 32bit address space, the same will happen to 64bit. And your fallback code has to match 100% of the desired functionality, and be tested as extensively, and in the long run is going to have a longer operational life with greater platform compat than the bit-stealing code. Easier to just do the work once, and move on.

    💬 0🔄 0⭐ 0
  • Sep 17, 2026, 1:39 AM

    @mcc @hyc It's very much not true, per my prior research into this exact topic, as someone who is implementing a programming language with tagged pointers. Many languages do this. I haven't had a lot of opportunity to explore hardware portability to other architectures in practice, but I can literally tell you from experience that AMD64 can handle 8 bit and 16 bit tagged pointers with the tag at the top or the bottom, all with performance similar enough that you have to run the hardware pretty ragged to tell the difference. I have graphs. Your instinct about applying rules before treating a tagged pointer as a real pointer is just... correct.

    Of course, I have the freedom to declare by fiat that someone using >56 bits of address space is doing something philosophically incorrect. Not everyone has that freedom. But I feel comfortable making that a design limitation of a general-purpose programming language, so 🤷‍♀️

    maddiem4.cc/blog/fuller-stack/

    💬 1🔄 0⭐ 0
  • 💬 0🔄 0⭐ 3
  • Sep 16, 2026, 10:15 PM

    @hyc

    On AMD64, the CPUID instruction will tell you whether the CPU supports 57-bit linear addresses and 5-level paging. Problem is, when a future processor supports 61-bit linear addresses, your code won't know that it must check CPUID again to find out.

    I understand the appeal of sparing every available bit — I cut my teeth on a 6502 and 32KiB of memory — but storing data in currently-unused bits of pointers is just saving up compatibility bugs for the future.

    Edit: I mistyped AMD64 as ARM64. Sorry. It's been a bad week!

    @mcc

    💬 0🔄 1⭐ 1