Login
You're viewing the discuss.systems public feed.
  • Oct 4, 2026, 9:36 AM

    @rygorous @GDCPresoReviews though the output space allocation strategies also vary by hardware. NVIDIA's current architectures do use a pre allocation (think shared memory) before the mesh shader is run. This is worst case outputs. (And also true for vertex shaders). As result it can limit occupancy.

    From that, the surviving subset is then passed through pipeline.

    NV doesn't support non 32-bit outputs, but one can use shader barycentrics and interpolate custom packed attributes.

    💬 1🔄 0⭐ 0

Replies

  • 💬 0🔄 0⭐ 1
  • Oct 4, 2026, 9:51 AM

    @pixeljetstream @GDCPresoReviews we did some experiments with this in the experimental LRB tess pipe; from underlying dynamics it was clear that below a certain number of quads per tri, the plane equation setup step (which we also had to do on "shader cores" since that was all we had!) wasn't worth the cost.

    We tried an alternative interpolation setup for PSOs (well, the internal equivalent) used for high tess where we did full 3D I,J,K barycentrics, K=1-I-J, and interp as

    K*v0+I*v1+J*v2

    💬 1🔄 0⭐ 0
  • Oct 4, 2026, 9:55 AM

    @pixeljetstream @GDCPresoReviews slightly more expensive interp (mul-mad-mad instead of mad-mad, essentially) and the pixel shader had to gather the tri attrs instead of a dedicated setup stage doing it, but a PS was in a better position to hide the gather latency than the dedicated setup did, because it had some reasonable other work to interleave it with.

    Dedicated setup was basically all gathers and then just a sub or two, then back to gathers, so constantly waiting on gathers.

    💬 1🔄 0⭐ 0
  • 💬 0🔄 0⭐ 0