Jun 30, 2025, 11:31 AM

This gibberish is me getting a simulation of the SDRAM chip used on the ULX3S working under a testbench. My goal is to write a very simple UART->SDRAM->UART dataflow and I was having data corruption issues that were (for beginner me) hard to track down. Now I can use the chip simulation to write some better code and hopefully get everything writing correctly. #fpga

Graph of signals. At the top for two related to a simulated UART showing data inputs. Next are several signals showing SDRAM write request and completion status as well as the data to write. Finally, some signals related to the commands requested of the SDRAM and the internal state of the SDRAM controller I'm using.