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  • Oct 13, 2026, 8:53 PM

    (the accesses in green are coming from the DMA peripheral, and the bus conflicts are happening when both DMA and the PPU are trying to put a value on the address bus)

    (i wonder how hot you could make a game boy SoC if you did this on purpose)

    (it's genuinely bewildering to keep track of which bus accesses from which components are possible under which conditions)

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Replies

  • Oct 13, 2026, 11:53 PM

    i think if i'm going to implement sprite rendering i might as well implement audio. sigh

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  • Oct 14, 2026, 3:36 PM

    i'm sure there's an option to turn on warnings about this, but a thing that sucks about cython is that leaving off a single type annotation on a function sets off a chain reaction in which anything that has the mis-annotated function in its call stack slows to a crawl (because now that function is using python values that have to be dynamically allocated and converted back and forth from C values). and then i end up having to comb through the generated C to find the problem

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  • Oct 14, 2026, 3:44 PM

    i am simultaneously (a) glad that i tried out cython for this project, because now i'm more familiar with how it works and behaves; and (b) convinced that you should basically never use cython. [alanis morissette voice] you live, you learn

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  • Oct 17, 2026, 7:05 PM

    i decided to take a break from the ppu and implement the link port. this seems like an area where there is not a lot of existing test infrastructure for gb emulators, e.g., neither the blarggh test suite nor the mooneye test suite address the link port at all (except for one esoteric timing test in the latter). (makes sense since to actually test the link port you'd have to run two emulators at once and have an agreed-upon protocol for how they should talk to each other, which is a big ask)

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  • Oct 17, 2026, 7:14 PM

    since my eventual (far distant) goal is to be able to run this emulator on a microcontroller that can replace the DMG SoC in a system otherwise using real game boy hardware, i'm realizing now that i should be implementing all of the external r/w signals (like the external data buses, or the link port clock pin) as tri-state values (i.e., asserting low, asserting high, not asserting anything) and not just as binary (zero or one). note to self, i guess!

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  • Oct 14, 2026, 4:15 PM

    @aparrish me not having heard of this: what's cython, an unholy fusion of python and C?
    me googling: oh my stars and garters

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  • Oct 14, 2026, 4:17 PM

    @horsewizard it's well intentioned, and it's amazing that it works as well as it does, but i can't help but feel that it is profoundly misguided

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