The V20 has a fairly clean design, with its own set of edge cases.
It's different from the 8088 in little ways, but in ways that were far less annoying to figure out.
trying to make diagrams of what is going on but i am bad at diagrams.
there's a suggestion of a newly discovered register - the queue read latch, but it could also just be something really strange and weird about the instruction queue timing. modelling a separate latch makes the cycles line up.

